Module 28 - A207a
A207a: Building an ITS Infrastructure Based on the Advanced Transportation Controller (ATC) 5201 Standard, Part 1 of 2
HTML of the Student Supplement
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(Extended Text Description: Large graphic cover page with dark blue background with the title in white letters "A207a: Building an ITS Infrastructure Based on the Advanced Transportation Controller (ATC) 5201 Standard Part 1 of 2" At the middle left is the "Standards ITS Training" logo with a white box and letters in blue and green. The words "Student Supplement" and "RITA Intelligent Transportation Systems Joint Program Office" in white lettering are directly underneath the logo. Three light blue lines move diagonally across the middle of the blue background.)
A207a: Building an ITS Infrastructure Based on the ATC 5201 Standard Part 1 of 2
Table of Contents
Introduction/Purpose - 2
Traffic Concepts - 2
Glossary - 4
Reference to Other Standards - 8
References - 8
Study Questions - 8
1. Introduction/Purpose
A207a: Building an ITS Infrastructure Based on the ATC 5201 Standard Part 1 of 2 is the first of two modules of the Professional Capacity Building (PCB) program on using the Advanced Transportation Controller (ATC) 5201 Standard. A207a explains the purpose of the ATC family of standards and identifies the basic components and operation of transportation field cabinet systems (TFCSs). This module provides the background information necessary to understand A207b: Building an ITS Infrastructure Based on the ATC 5201 Standard Part 2 of 2.
2. Traffic Concepts
Intersection Actuation - The extent to which an intersection is equipped for vehicle detection.
(Extended Text Description: This graphic consists of three graphics each representing a 4 way intersection. The intersection graphics are arranged such that two are evenly distributed across the page. The third intersection graphic is below the first two and aligned center on the page. Each graphic is depicted as two two-lane roads intersecting perpendicularly North/South and East/West in the shape of a cross (it is assumed that upward is north). There is a centerline on each road to differentiate the northbound lane from the southbound lane and the eastbound lane from the westbound lane. The area where the roads cross (center of the cross) is blank (no lines running through it). In the bottom graphic, the southbound, northbound, westbound, and eastbound approaches to the intersection contain rectangles extending across the width of the lane (total four lanes). The rectangles have one edge at the point where the blank center area begins and extends back into the lane about 1 ½ times their width. This graphic is labeled "Actuated." The graphic to the upper right has the rectangles on the southbound and northbound directions only. This graphic is labeled "Semi-Actuated." The graphic on the upper left does not contain any of the rectangles. This graphic is labeled "Non-Actuated.")
Figure 1
Cycle - The time required for one complete revolution of the timing dial (old definition). One complete sequence of signal indications.
Interval - Any one of the several divisions of the time cycle during which signal indications do not change. Examples:
Phase - Any combination of traffic movements receiving right-of-way simultaneously during one or more intervals
Overlap - A traffic movement timed concurrently with one or more phases (parent phases). Typically, the yellow and red clearance timing of the overlap is equal to that of the phase terminating the overlap.
Standard Quad or 8-Phase Intersection. The odd numbered phases represent left turn movements. The even numbered phases represent through movements. Overlaps are indicated by the plus signs and indicate that the right arrow would appear during the timing of the two phases indicated. Example: The overlap 08 + 01 would be allowed during the timing of 08 and 01. No U-turns on left arrow allowed.
(Extended Text Description: This is a graphic representing of a 4 way intersection. It is depicted as two four-lane roads intersecting perpendicularly North/South and East/West in the shape of a large cross (it is assumed that upward is north). There is a center median about the same width as the lanes on each road to differentiate the northbound lanes from the southbound lanes and the eastbound lanes from the westbound lanes. On each side of the median are parallel dotted lines to identify the two lanes on each side. The area where the roads cross (center of the cross) is blank (no lines running through it). For each of the southbound, northbound, westbound, and eastbound approaches to the intersection, the center medians narrow to provide an additional left turn lane for each approach (total 4). The straight through lanes and adjacent left turn lanes on each approach are separated by a dotted line. Each approach has its lanes identified as described below:
)
Figure 2
Ring - Consists of two or more sequentially timed and individually selected conflicting phases so arranged as to occur in an established order.
Barrier - A reference point in the preferred sequence of a multi-ring controller at which all rings are interlocked. Barriers assure there will be no concurrent selection and timing of conflicting phases for traffic movements are in different rings. All rings cross the barrier simultaneously to select and time phases on the other side.
Concurrent Groups - All of the phases between two barriers. Typically, they are the left turn and through movements on a single street.
Dual Ring Operation for a Standard Quad - See diagram below. There are two rings. The first consists of phases 1-4 and the second consists of phases 5-8. A phase in Ring 1 can time with a phase in Ring 2 provided they are a part of the same concurrent group.
(Extended Text Description: This is a graphic representing the flow of service for each of the turning movements in a 4 way intersection. There are eight squares arranged in a two columns and four rows all evenly spaced. Above the left column of squares is a label "RING 1." Above the right column of squares is a label "RING 2." There is a dashed line extending vertically from between the labels to the bottom of the graphic. The dashed line is centered between the columns of squares. There is a horizontal dashed line extending across the graphic evenly between the second and third row of squares. The line is labeled "BARRIER." There is a second such dashed line and label extending across the graphic below the fourth row of squares. To the right of the graphic is a large right bracket highlighting the top four squares (above the first barrier line) with the label "CONCURRENT GROUP." To the right of the graphic is a large right bracket highlighting the bottom four squares (below the first barrier line) labeled "CONCURRENT GROUP."
Each square contains a number and an arrow. The left column of squares contains the following (top to bottom):
The right column of squares contains the following (top to bottom):
There are solid lines connecting the numbered squares as follows:
)
Figure 3
3. Glossary
Term | Definition |
---|---|
AASHTO | American Association of State Highway and Transportation Officials |
AC | Alternating Current |
AC- | 120 VAC, 60 Hz neutral (grounded return to the power source) |
AC+ | 120 VAC, 60 Hz line source (ungrounded) |
ANSI | American National Standard Institute |
ASCII | American Standard Code for Information Interchange |
Assembly | A complete machine, structure, or unit of a machine that was manufactured by fitting together parts and/or modules |
ASTM | American Society for Testing and Materials |
ATC | Advanced Transportation Controller |
AWG | American Wire Gage |
BSP | Board Support Package |
Cabinet | An outdoor enclosure generally housing the controller unit and associated equipment |
Caltrans | California Department of Transportation |
CD | Carrier Detect |
Component | Any electrical or electronic device |
CPU | Central Processing Unit |
CTS | Clear to send (data) |
CU | Controller Unit, that portion of the controller assembly devoted to the operational control of the logic decisions programmed into the assembly |
DAT | Design Acceptance Testing |
DC | Direct Current |
DCD | Data Carrier Detect (receive line signal detector) |
DRAM | Dynamic Random Access Memory |
EEPROM | Electrically Erasable Programmable Read-Only Memory |
EG | Equipment Ground |
EIA | Electronic Industries Association |
EL | Electro-luminescent |
EMI | Electromagnetic Interference |
ENET | Ethernet |
EPROM | Ultraviolet Erasable, Programmable, Read-Only Memory |
Equal | Connectors: comply to physical dimensions, contact material, plating and method of connection. Devices: comply to function, pin out, electrical and operating parameter requirements, access times and interface parameters of the specified device |
ETL | Electrical Testing Laboratories, Inc. |
FCU | Field Control Unit |
Firmware | A computer program or software stored permanently in PROM, EPROM, ROM, or semi-permanently in EEPROM |
FLASH | A form of EEPROM that allows multiple memory locations to be erased or written in one programming operation. It is solid-state, permanent, and non-volatile memory typically having fast access and read/write cycles |
FPA | Front Panel Assembly |
FSK | Frequency Shift Keying |
HDLC | High-level Data Link Control |
I/O | Input/Output |
IEEE | Institute of Electrical and Electronics Engineers |
IP | Internet Protocol |
ISO | International Standards Organization |
ITE | Institute of Transportation Engineers |
ITS | Intelligent Transportation Systems |
Jumper | A means of connecting/disconnecting two or more conductors by soldering/desoldering a conductive wire or by PCB post jumper |
Keyed | Means by which like connectors can be physically altered to prevent improper insertion |
LCD | Liquid Crystal Display |
LED | Light Emitting Diode |
LOGIC | Negative logic convention (Ground True) state |
logic-level | HCT or equivalent TTL – compatible voltage interface levels |
lsb | Least Significant Bit |
LSB | Least Significant Byte |
MIPS | Million Instructions Per Second |
Module | A functional unit that plugs into an assembly |
msb | Most Significant Bit |
MS | Military Specification, Mil-Spec, or Mil-Standard |
MSB | Most Significant Byte |
NA | Presently Not Assigned. Cannot be used by the contractor for other purposes. |
NEMA | National Electrical Manufacturer's Association |
NETA | National Electrical Testing Association, Inc. |
NLSB | Next Least Significant Byte |
NMSB | Next Most Significant Byte |
NTCIP | National Transportation Communication for ITS Protocols |
OST | Operating System Time |
NYSDOT | New York State Department of Transportation |
O/S | Operating System |
Open System | Standardized hardware interfaces in a module |
PCB | Printed Circuit Board |
PDA | Personal Data Assistant (electronic) |
RAM | Random Access Memory |
RF | Radio Frequency |
RMS | Root mean square |
ROM | Read only memory |
RTC | Real Time Clock |
RTS | Request to send (data) |
RX | Abbreviation for “Receive” when used to describe communication signals. Typically a prefix for other character(s). |
RXC | Receive Clock |
RXD | Receive Data |
SDLC | Synchronous Data Link Control |
SP | Serial Port |
SPI | Serial Peripheral Interface |
SRAM | Static Random Access Memory |
TEES | Transportation Electrical Equipment Specifications |
TMC | Transportation Management Center |
TOD | Time Of Day Clock |
TTL | Transistor-Transistor Logic |
TX | Abbreviation for “Transmit” when used to describe communication signals. Typically a prefix for other character(s). |
TXC | Transmit Clock |
TXD | Transmit Data |
UL | Underwriter's Laboratories, Inc. |
USB | Universal Serial Bus |
VAC | Volts Alternating Current |
VDC | Volts Direct Current |
WDT | Watchdog Timer: A monitoring circuit, external to the device watched, which senses an Output Line from the device and reacts |
4. Reference to Other Standards
5. References
6. Study Questions
Participant Questions Included in Presentation